1. Field of the Invention
The present invention relates to an electrical interconnection arrangement for making connection between electronic devices. More particularly, the present invention relates to a multilayer interposer arrangement for making connection between semiconductor chip and laminate chip carrier.
2. Background and Related Art
One of the problems encountered with semiconductor chip connections to the next level of packaging is the high stress on the interconnections caused by coefficient of thermal expansion (CTE) mismatch. The CTE thermal mismatch is particularly large where the chip is connected to laminate chip carriers typically made of material similar to an epoxy circuit board material. As circuit densities in chips increase, so does the heat generated by these chips thereby compounding the problem with larger temperature variations in its thermal cycle. In addition, certain applications, such as flip chip applications, have required encapsulation to ensure a reliable flip chip interconnection in the solder joints. Such encapsulation typically employs a high strength epoxy which acts to bond the chip to the laminate chip carrier. This bonding of chip to chip carrier reduces solder joint stress during thermal cycling but causes the chip itself to be put under cyclical high internal stress eventually leading to chip cracking, delamination and device breakdown.
The above described high internal stresses on the chip are generally attributed to the fact that the bonding of chip to laminate chip carrier acts to cause this composite of materials to act like a xe2x80x9cbimetallicxe2x80x9d element wherein the composite bends upon heating due to the different CTE of the materials. As a result of the large thermal mismatch between chip and laminate chip carrier, the cyclical bending over time causes device failure. In this regard, the CTE for a typical semiconductor chip may be in the order of 3 micro inches per inch per degree Centigrade while a typical laminate chip carrier is around six times that amount. Thus, although the use of encapsulation is to prevent the C-4 connections from detaching due to fatigue and fracturing over thermal cycling, the bonding action of the encapsulation in itself acts to cause the chips to fracture and separate from the chip carrier.
In general, others have attempted to address the problems caused by CTE mismatch of materials in IC packaging by providing various interposing structures that attempt to compensate or reduce the mismatch of CTE. For example, two or more layers of materials with varying CTEs may be employed to form an interposing layer between one level of packaging and the next, with the layers having different CTEs such that the layer contacting one level of packaging is selected to have a CTE which more closely matches the CTE of that level while the layer contacting the next level of packaging has a CTE more closely matching that level. An example of such an arrangement is described in U.S. Pat. No. 5,386,341 to Olson, et al. The difficulty with arrangements, such as in Olson, et al., is that it is costly to fabricate and difficult to assemble, and does not readily lend itself to microminatization. In addition, various efforts have also been made to use interposing layers which are flexible in nature such as to reduce the stress on electrical interconnections during thermal cycling created by thermal mismatch. Examples of such an approach are taught in U.S. Pat. No. 4,937,707 to McBride, et al., and U.S. Pat. No. 5,362,656 to McMahon. However, as with Olson, et al. the difficulty with such approaches is they are costly to fabricate and do not readily lend themselves to microminatization.
In accordance with the teachings of the present invention, internal stresses in chips and their electrical interconnection caused by either CTE mismatch or encapsulation and bonding of chips to laminate chip carriers are overcome through the use of a multilayer CTE compensated interposer having an array of connectors extending therethrough and positioned between chip contacts and laminate chip carrier contacts. The multilayer CTE compensated interposer acts to provide both a signal and power redistribution chip carrier and CTE matching between chip and laminate carrier.
The CTE compensated interposer of the present invention comprises a three layer laminated arrangement of different materials with each layer having significantly different physical properties from the others. The interposer has a patterned array of conductive vias matching the array of C4 solder contacts on the chip and solder contacts on the laminate chip carrier. The top interposer layer, adjacent the chip, is made of a high elastic modulus stiff material, such as ceramic, which closely matches the CTE of the chip. The bottom interposer layer, adjacent the laminate, is made from a thin core material with layers of metallurgy formed thereon having a substantially lower elastic modulus than the top layer and a composite CTE that closely matches the CTE of the laminate. The layer intermediate the top layer and bottom layer is made of a core material with layers of metallurgy formed thereon that may have an even lower elastic modulus than the bottom layer and a composite CTE between the top and bottom layers. The high modulus, stiff, top layer will prevent bending which might otherwise occur with materials having differing CTEs laminated together. Since a close CTE match occurs between top layer and chip and bottom layer and laminate, little internal stress or fracturing due to thermal cycling occurs at the solder joint connections to these layers. If a low modulus intermediate layer is used, it may act to some degree as a shearable adhesive to provide the xe2x80x9cgivexe2x80x9d or resiliance between top and bottom layers. The layers of metallurgy on the intermediate and bottom layers act to provide both a means of signal and power redistribution and a means to modify the CTE of the respective layers.
In one fabrication process, when plated vias of the interposer are aligned with C-4 solder balls on a flip chip die, upon heating the vias become filled with solder while becoming electrically connected to the chip die. The other ends of the vias are attached to the chip carrier laminate by a low melt solder.
Accordingly, it is an object of the present invention to provide an improved integrated circuit device package and method of making same.
It is another object of the present invention to provide improved electronic device interconnection and method of making same.
It is a further object of the present invention to provide improved electronic interconnection between semiconductor chip and chip carrier.
It is yet a further object of the present invention to provide an improved electronic interconnection between semiconductor chip and laminate chip carrier such as to reduce internal stress in both the chip and the electrical interconnections between chip and laminate chip carrier.
It is still yet a further object of the present invention to provide a CTE compensated interposer arrangement between chip and laminate chip carrier which allows the chip to be connected to the laminate chip carrier either with or without encapsulation of the interconnection points.
It is another object of the present invention to provide a method and apparatus for making electrical interconnection of chip directly to printed circuit board laminate.
It is yet another object of the present invention to provide an interposer arrangement of multiple layers of different materials having selected CTEs and elastic moduli arranged to reduce stress, cracking and delamination due to thermal mismatch.
It is still another object of the present invention to provide an interposer which functions as both CTE compensation means and signal and power redistribution means.
These foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings, wherein like reference members represent like parts of the invention.